;
; File Name: cyfitteriar.inc
; 
; PSoC Creator  4.2
;
; Description:
; 
;
;-------------------------------------------------------------------------------
; Copyright (c) 2007-2018 Cypress Semiconductor.  All rights reserved.
; You may use this file only in accordance with the license, terms, conditions, 
; disclaimers, and limitations in the end user license agreement accompanying 
; the software package with which this file was provided.
;-------------------------------------------------------------------------------

#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar_trm.inc

/* PWM */
PWM_BUZZ__0__DR EQU CYREG_GPIO_PRT1_DR
PWM_BUZZ__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
PWM_BUZZ__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
PWM_BUZZ__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
PWM_BUZZ__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
PWM_BUZZ__0__HSIOM_MASK EQU 0x0000000F
PWM_BUZZ__0__HSIOM_SHIFT EQU 0
PWM_BUZZ__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
PWM_BUZZ__0__INTR EQU CYREG_GPIO_PRT1_INTR
PWM_BUZZ__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
PWM_BUZZ__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
PWM_BUZZ__0__MASK EQU 0x01
PWM_BUZZ__0__PC EQU CYREG_GPIO_PRT1_PC
PWM_BUZZ__0__PC2 EQU CYREG_GPIO_PRT1_PC2
PWM_BUZZ__0__PORT EQU 1
PWM_BUZZ__0__PS EQU CYREG_GPIO_PRT1_PS
PWM_BUZZ__0__SHIFT EQU 0
PWM_BUZZ__DR EQU CYREG_GPIO_PRT1_DR
PWM_BUZZ__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
PWM_BUZZ__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
PWM_BUZZ__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
PWM_BUZZ__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
PWM_BUZZ__INTR EQU CYREG_GPIO_PRT1_INTR
PWM_BUZZ__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
PWM_BUZZ__INTSTAT EQU CYREG_GPIO_PRT1_INTR
PWM_BUZZ__MASK EQU 0x01
PWM_BUZZ__PC EQU CYREG_GPIO_PRT1_PC
PWM_BUZZ__PC2 EQU CYREG_GPIO_PRT1_PC2
PWM_BUZZ__PORT EQU 1
PWM_BUZZ__PS EQU CYREG_GPIO_PRT1_PS
PWM_BUZZ__SHIFT EQU 0
PWM_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT2_CC
PWM_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT2_CC_BUFF
PWM_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT2_COUNTER
PWM_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT2_CTRL
PWM_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT2_INTR
PWM_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT2_INTR_MASK
PWM_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT2_INTR_MASKED
PWM_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT2_INTR_SET
PWM_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT2_PERIOD
PWM_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT2_PERIOD_BUFF
PWM_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT2_STATUS
PWM_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x04
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 2
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x400
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 10
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x4000000
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 26
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x40000
PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 18
PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x04
PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 2
PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x04
PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 2
PWM_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 2
PWM_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT2_TR_CTRL0
PWM_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT2_TR_CTRL1
PWM_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT2_TR_CTRL2

/* LED1 */
LED1__0__DR EQU CYREG_GPIO_PRT1_DR
LED1__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LED1__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LED1__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LED1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
LED1__0__HSIOM_MASK EQU 0xF0000000
LED1__0__HSIOM_SHIFT EQU 28
LED1__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LED1__0__INTR EQU CYREG_GPIO_PRT1_INTR
LED1__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LED1__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LED1__0__MASK EQU 0x80
LED1__0__PC EQU CYREG_GPIO_PRT1_PC
LED1__0__PC2 EQU CYREG_GPIO_PRT1_PC2
LED1__0__PORT EQU 1
LED1__0__PS EQU CYREG_GPIO_PRT1_PS
LED1__0__SHIFT EQU 7
LED1__DR EQU CYREG_GPIO_PRT1_DR
LED1__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LED1__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LED1__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LED1__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LED1__INTR EQU CYREG_GPIO_PRT1_INTR
LED1__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LED1__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LED1__MASK EQU 0x80
LED1__PC EQU CYREG_GPIO_PRT1_PC
LED1__PC2 EQU CYREG_GPIO_PRT1_PC2
LED1__PORT EQU 1
LED1__PS EQU CYREG_GPIO_PRT1_PS
LED1__SHIFT EQU 7

/* LED2 */
LED2__0__DR EQU CYREG_GPIO_PRT0_DR
LED2__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED2__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED2__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED2__0__HSIOM_MASK EQU 0x000000F0
LED2__0__HSIOM_SHIFT EQU 4
LED2__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED2__0__INTR EQU CYREG_GPIO_PRT0_INTR
LED2__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED2__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED2__0__MASK EQU 0x02
LED2__0__PC EQU CYREG_GPIO_PRT0_PC
LED2__0__PC2 EQU CYREG_GPIO_PRT0_PC2
LED2__0__PORT EQU 0
LED2__0__PS EQU CYREG_GPIO_PRT0_PS
LED2__0__SHIFT EQU 1
LED2__DR EQU CYREG_GPIO_PRT0_DR
LED2__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED2__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED2__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED2__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED2__INTR EQU CYREG_GPIO_PRT0_INTR
LED2__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED2__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED2__MASK EQU 0x02
LED2__PC EQU CYREG_GPIO_PRT0_PC
LED2__PC2 EQU CYREG_GPIO_PRT0_PC2
LED2__PORT EQU 0
LED2__PS EQU CYREG_GPIO_PRT0_PS
LED2__SHIFT EQU 1

/* LED3 */
LED3__0__DR EQU CYREG_GPIO_PRT0_DR
LED3__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED3__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED3__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED3__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED3__0__HSIOM_MASK EQU 0x0000000F
LED3__0__HSIOM_SHIFT EQU 0
LED3__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED3__0__INTR EQU CYREG_GPIO_PRT0_INTR
LED3__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED3__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED3__0__MASK EQU 0x01
LED3__0__PC EQU CYREG_GPIO_PRT0_PC
LED3__0__PC2 EQU CYREG_GPIO_PRT0_PC2
LED3__0__PORT EQU 0
LED3__0__PS EQU CYREG_GPIO_PRT0_PS
LED3__0__SHIFT EQU 0
LED3__DR EQU CYREG_GPIO_PRT0_DR
LED3__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED3__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED3__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED3__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED3__INTR EQU CYREG_GPIO_PRT0_INTR
LED3__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED3__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED3__MASK EQU 0x01
LED3__PC EQU CYREG_GPIO_PRT0_PC
LED3__PC2 EQU CYREG_GPIO_PRT0_PC2
LED3__PORT EQU 0
LED3__PS EQU CYREG_GPIO_PRT0_PS
LED3__SHIFT EQU 0

/* LED4 */
LED4__0__DR EQU CYREG_GPIO_PRT4_DR
LED4__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
LED4__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
LED4__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
LED4__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
LED4__0__HSIOM_MASK EQU 0x0000F000
LED4__0__HSIOM_SHIFT EQU 12
LED4__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
LED4__0__INTR EQU CYREG_GPIO_PRT4_INTR
LED4__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
LED4__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
LED4__0__MASK EQU 0x08
LED4__0__PC EQU CYREG_GPIO_PRT4_PC
LED4__0__PC2 EQU CYREG_GPIO_PRT4_PC2
LED4__0__PORT EQU 4
LED4__0__PS EQU CYREG_GPIO_PRT4_PS
LED4__0__SHIFT EQU 3
LED4__DR EQU CYREG_GPIO_PRT4_DR
LED4__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
LED4__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
LED4__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
LED4__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
LED4__INTR EQU CYREG_GPIO_PRT4_INTR
LED4__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
LED4__INTSTAT EQU CYREG_GPIO_PRT4_INTR
LED4__MASK EQU 0x08
LED4__PC EQU CYREG_GPIO_PRT4_PC
LED4__PC2 EQU CYREG_GPIO_PRT4_PC2
LED4__PORT EQU 4
LED4__PS EQU CYREG_GPIO_PRT4_PS
LED4__SHIFT EQU 3

/* RXDI */
RXDI__0__DR EQU CYREG_GPIO_PRT4_DR
RXDI__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
RXDI__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
RXDI__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
RXDI__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
RXDI__0__HSIOM_MASK EQU 0x0000000F
RXDI__0__HSIOM_SHIFT EQU 0
RXDI__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
RXDI__0__INTR EQU CYREG_GPIO_PRT4_INTR
RXDI__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
RXDI__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
RXDI__0__MASK EQU 0x01
RXDI__0__PC EQU CYREG_GPIO_PRT4_PC
RXDI__0__PC2 EQU CYREG_GPIO_PRT4_PC2
RXDI__0__PORT EQU 4
RXDI__0__PS EQU CYREG_GPIO_PRT4_PS
RXDI__0__SHIFT EQU 0
RXDI__DR EQU CYREG_GPIO_PRT4_DR
RXDI__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
RXDI__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
RXDI__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
RXDI__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
RXDI__INTR EQU CYREG_GPIO_PRT4_INTR
RXDI__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
RXDI__INTSTAT EQU CYREG_GPIO_PRT4_INTR
RXDI__MASK EQU 0x01
RXDI__PC EQU CYREG_GPIO_PRT4_PC
RXDI__PC2 EQU CYREG_GPIO_PRT4_PC2
RXDI__PORT EQU 4
RXDI__PS EQU CYREG_GPIO_PRT4_PS
RXDI__SHIFT EQU 0

/* TXDI */
TXDI__0__DR EQU CYREG_GPIO_PRT4_DR
TXDI__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
TXDI__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
TXDI__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
TXDI__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
TXDI__0__HSIOM_MASK EQU 0x000000F0
TXDI__0__HSIOM_SHIFT EQU 4
TXDI__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
TXDI__0__INTR EQU CYREG_GPIO_PRT4_INTR
TXDI__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
TXDI__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
TXDI__0__MASK EQU 0x02
TXDI__0__PC EQU CYREG_GPIO_PRT4_PC
TXDI__0__PC2 EQU CYREG_GPIO_PRT4_PC2
TXDI__0__PORT EQU 4
TXDI__0__PS EQU CYREG_GPIO_PRT4_PS
TXDI__0__SHIFT EQU 1
TXDI__DR EQU CYREG_GPIO_PRT4_DR
TXDI__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
TXDI__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
TXDI__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
TXDI__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
TXDI__INTR EQU CYREG_GPIO_PRT4_INTR
TXDI__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
TXDI__INTSTAT EQU CYREG_GPIO_PRT4_INTR
TXDI__MASK EQU 0x02
TXDI__PC EQU CYREG_GPIO_PRT4_PC
TXDI__PC2 EQU CYREG_GPIO_PRT4_PC2
TXDI__PORT EQU 4
TXDI__PS EQU CYREG_GPIO_PRT4_PS
TXDI__SHIFT EQU 1

/* UART */
UART_rx__0__DR EQU CYREG_GPIO_PRT0_DR
UART_rx__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
UART_rx__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
UART_rx__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
UART_rx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
UART_rx__0__HSIOM_GPIO EQU 0
UART_rx__0__HSIOM_I2C EQU 14
UART_rx__0__HSIOM_I2C_SCL EQU 14
UART_rx__0__HSIOM_MASK EQU 0x000F0000
UART_rx__0__HSIOM_SHIFT EQU 16
UART_rx__0__HSIOM_SPI EQU 15
UART_rx__0__HSIOM_SPI_MOSI EQU 15
UART_rx__0__HSIOM_UART EQU 9
UART_rx__0__HSIOM_UART_RX EQU 9
UART_rx__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_rx__0__INTR EQU CYREG_GPIO_PRT0_INTR
UART_rx__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_rx__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
UART_rx__0__MASK EQU 0x10
UART_rx__0__PC EQU CYREG_GPIO_PRT0_PC
UART_rx__0__PC2 EQU CYREG_GPIO_PRT0_PC2
UART_rx__0__PORT EQU 0
UART_rx__0__PS EQU CYREG_GPIO_PRT0_PS
UART_rx__0__SHIFT EQU 4
UART_rx__DR EQU CYREG_GPIO_PRT0_DR
UART_rx__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
UART_rx__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
UART_rx__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
UART_rx__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_rx__INTR EQU CYREG_GPIO_PRT0_INTR
UART_rx__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_rx__INTSTAT EQU CYREG_GPIO_PRT0_INTR
UART_rx__MASK EQU 0x10
UART_rx__PC EQU CYREG_GPIO_PRT0_PC
UART_rx__PC2 EQU CYREG_GPIO_PRT0_PC2
UART_rx__PORT EQU 0
UART_rx__PS EQU CYREG_GPIO_PRT0_PS
UART_rx__SHIFT EQU 4
UART_SCB__CTRL EQU CYREG_SCB1_CTRL
UART_SCB__EZ_DATA0 EQU CYREG_SCB1_EZ_DATA0
UART_SCB__EZ_DATA1 EQU CYREG_SCB1_EZ_DATA1
UART_SCB__EZ_DATA10 EQU CYREG_SCB1_EZ_DATA10
UART_SCB__EZ_DATA11 EQU CYREG_SCB1_EZ_DATA11
UART_SCB__EZ_DATA12 EQU CYREG_SCB1_EZ_DATA12
UART_SCB__EZ_DATA13 EQU CYREG_SCB1_EZ_DATA13
UART_SCB__EZ_DATA14 EQU CYREG_SCB1_EZ_DATA14
UART_SCB__EZ_DATA15 EQU CYREG_SCB1_EZ_DATA15
UART_SCB__EZ_DATA16 EQU CYREG_SCB1_EZ_DATA16
UART_SCB__EZ_DATA17 EQU CYREG_SCB1_EZ_DATA17
UART_SCB__EZ_DATA18 EQU CYREG_SCB1_EZ_DATA18
UART_SCB__EZ_DATA19 EQU CYREG_SCB1_EZ_DATA19
UART_SCB__EZ_DATA2 EQU CYREG_SCB1_EZ_DATA2
UART_SCB__EZ_DATA20 EQU CYREG_SCB1_EZ_DATA20
UART_SCB__EZ_DATA21 EQU CYREG_SCB1_EZ_DATA21
UART_SCB__EZ_DATA22 EQU CYREG_SCB1_EZ_DATA22
UART_SCB__EZ_DATA23 EQU CYREG_SCB1_EZ_DATA23
UART_SCB__EZ_DATA24 EQU CYREG_SCB1_EZ_DATA24
UART_SCB__EZ_DATA25 EQU CYREG_SCB1_EZ_DATA25
UART_SCB__EZ_DATA26 EQU CYREG_SCB1_EZ_DATA26
UART_SCB__EZ_DATA27 EQU CYREG_SCB1_EZ_DATA27
UART_SCB__EZ_DATA28 EQU CYREG_SCB1_EZ_DATA28
UART_SCB__EZ_DATA29 EQU CYREG_SCB1_EZ_DATA29
UART_SCB__EZ_DATA3 EQU CYREG_SCB1_EZ_DATA3
UART_SCB__EZ_DATA30 EQU CYREG_SCB1_EZ_DATA30
UART_SCB__EZ_DATA31 EQU CYREG_SCB1_EZ_DATA31
UART_SCB__EZ_DATA4 EQU CYREG_SCB1_EZ_DATA4
UART_SCB__EZ_DATA5 EQU CYREG_SCB1_EZ_DATA5
UART_SCB__EZ_DATA6 EQU CYREG_SCB1_EZ_DATA6
UART_SCB__EZ_DATA7 EQU CYREG_SCB1_EZ_DATA7
UART_SCB__EZ_DATA8 EQU CYREG_SCB1_EZ_DATA8
UART_SCB__EZ_DATA9 EQU CYREG_SCB1_EZ_DATA9
UART_SCB__I2C_CFG EQU CYREG_SCB1_I2C_CFG
UART_SCB__I2C_CTRL EQU CYREG_SCB1_I2C_CTRL
UART_SCB__I2C_M_CMD EQU CYREG_SCB1_I2C_M_CMD
UART_SCB__I2C_S_CMD EQU CYREG_SCB1_I2C_S_CMD
UART_SCB__I2C_STATUS EQU CYREG_SCB1_I2C_STATUS
UART_SCB__INTR_CAUSE EQU CYREG_SCB1_INTR_CAUSE
UART_SCB__INTR_I2C_EC EQU CYREG_SCB1_INTR_I2C_EC
UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB1_INTR_I2C_EC_MASK
UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB1_INTR_I2C_EC_MASKED
UART_SCB__INTR_M EQU CYREG_SCB1_INTR_M
UART_SCB__INTR_M_MASK EQU CYREG_SCB1_INTR_M_MASK
UART_SCB__INTR_M_MASKED EQU CYREG_SCB1_INTR_M_MASKED
UART_SCB__INTR_M_SET EQU CYREG_SCB1_INTR_M_SET
UART_SCB__INTR_RX EQU CYREG_SCB1_INTR_RX
UART_SCB__INTR_RX_MASK EQU CYREG_SCB1_INTR_RX_MASK
UART_SCB__INTR_RX_MASKED EQU CYREG_SCB1_INTR_RX_MASKED
UART_SCB__INTR_RX_SET EQU CYREG_SCB1_INTR_RX_SET
UART_SCB__INTR_S EQU CYREG_SCB1_INTR_S
UART_SCB__INTR_S_MASK EQU CYREG_SCB1_INTR_S_MASK
UART_SCB__INTR_S_MASKED EQU CYREG_SCB1_INTR_S_MASKED
UART_SCB__INTR_S_SET EQU CYREG_SCB1_INTR_S_SET
UART_SCB__INTR_SPI_EC EQU CYREG_SCB1_INTR_SPI_EC
UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB1_INTR_SPI_EC_MASK
UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB1_INTR_SPI_EC_MASKED
UART_SCB__INTR_TX EQU CYREG_SCB1_INTR_TX
UART_SCB__INTR_TX_MASK EQU CYREG_SCB1_INTR_TX_MASK
UART_SCB__INTR_TX_MASKED EQU CYREG_SCB1_INTR_TX_MASKED
UART_SCB__INTR_TX_SET EQU CYREG_SCB1_INTR_TX_SET
UART_SCB__RX_CTRL EQU CYREG_SCB1_RX_CTRL
UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB1_RX_FIFO_CTRL
UART_SCB__RX_FIFO_RD EQU CYREG_SCB1_RX_FIFO_RD
UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB1_RX_FIFO_RD_SILENT
UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB1_RX_FIFO_STATUS
UART_SCB__RX_MATCH EQU CYREG_SCB1_RX_MATCH
UART_SCB__SPI_CTRL EQU CYREG_SCB1_SPI_CTRL
UART_SCB__SPI_STATUS EQU CYREG_SCB1_SPI_STATUS
UART_SCB__SS0_POSISTION EQU 0
UART_SCB__SS1_POSISTION EQU 1
UART_SCB__SS2_POSISTION EQU 2
UART_SCB__SS3_POSISTION EQU 3
UART_SCB__STATUS EQU CYREG_SCB1_STATUS
UART_SCB__TX_CTRL EQU CYREG_SCB1_TX_CTRL
UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB1_TX_FIFO_CTRL
UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB1_TX_FIFO_STATUS
UART_SCB__TX_FIFO_WR EQU CYREG_SCB1_TX_FIFO_WR
UART_SCB__UART_CTRL EQU CYREG_SCB1_UART_CTRL
UART_SCB__UART_FLOW_CTRL EQU CYREG_SCB1_UART_FLOW_CTRL
UART_SCB__UART_RX_CTRL EQU CYREG_SCB1_UART_RX_CTRL
UART_SCB__UART_RX_STATUS EQU CYREG_SCB1_UART_RX_STATUS
UART_SCB__UART_TX_CTRL EQU CYREG_SCB1_UART_TX_CTRL
UART_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
UART_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
UART_SCB_IRQ__INTC_MASK EQU 0x100
UART_SCB_IRQ__INTC_NUMBER EQU 8
UART_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0
UART_SCB_IRQ__INTC_PRIOR_NUM EQU 3
UART_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR2
UART_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
UART_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR
UART_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL1
UART_SCBCLK__DIV_ID EQU 0x00000043
UART_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL3
UART_SCBCLK__PA_DIV_ID EQU 0x000000FF
UART_tx__0__DR EQU CYREG_GPIO_PRT0_DR
UART_tx__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
UART_tx__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
UART_tx__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
UART_tx__0__HSIOM_GPIO EQU 0
UART_tx__0__HSIOM_I2C EQU 14
UART_tx__0__HSIOM_I2C_SDA EQU 14
UART_tx__0__HSIOM_MASK EQU 0x00F00000
UART_tx__0__HSIOM_SHIFT EQU 20
UART_tx__0__HSIOM_SPI EQU 15
UART_tx__0__HSIOM_SPI_MISO EQU 15
UART_tx__0__HSIOM_UART EQU 9
UART_tx__0__HSIOM_UART_TX EQU 9
UART_tx__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_tx__0__INTR EQU CYREG_GPIO_PRT0_INTR
UART_tx__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_tx__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
UART_tx__0__MASK EQU 0x20
UART_tx__0__PC EQU CYREG_GPIO_PRT0_PC
UART_tx__0__PC2 EQU CYREG_GPIO_PRT0_PC2
UART_tx__0__PORT EQU 0
UART_tx__0__PS EQU CYREG_GPIO_PRT0_PS
UART_tx__0__SHIFT EQU 5
UART_tx__DR EQU CYREG_GPIO_PRT0_DR
UART_tx__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
UART_tx__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
UART_tx__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
UART_tx__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_tx__INTR EQU CYREG_GPIO_PRT0_INTR
UART_tx__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
UART_tx__INTSTAT EQU CYREG_GPIO_PRT0_INTR
UART_tx__MASK EQU 0x20
UART_tx__PC EQU CYREG_GPIO_PRT0_PC
UART_tx__PC2 EQU CYREG_GPIO_PRT0_PC2
UART_tx__PORT EQU 0
UART_tx__PS EQU CYREG_GPIO_PRT0_PS
UART_tx__SHIFT EQU 5

/* COMM1 */
COMM1__0__DR EQU CYREG_GPIO_PRT0_DR
COMM1__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
COMM1__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
COMM1__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
COMM1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
COMM1__0__HSIOM_MASK EQU 0x0000F000
COMM1__0__HSIOM_SHIFT EQU 12
COMM1__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
COMM1__0__INTR EQU CYREG_GPIO_PRT0_INTR
COMM1__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
COMM1__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
COMM1__0__MASK EQU 0x08
COMM1__0__PC EQU CYREG_GPIO_PRT0_PC
COMM1__0__PC2 EQU CYREG_GPIO_PRT0_PC2
COMM1__0__PORT EQU 0
COMM1__0__PS EQU CYREG_GPIO_PRT0_PS
COMM1__0__SHIFT EQU 3
COMM1__DR EQU CYREG_GPIO_PRT0_DR
COMM1__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
COMM1__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
COMM1__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
COMM1__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
COMM1__INTR EQU CYREG_GPIO_PRT0_INTR
COMM1__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
COMM1__INTSTAT EQU CYREG_GPIO_PRT0_INTR
COMM1__MASK EQU 0x08
COMM1__PC EQU CYREG_GPIO_PRT0_PC
COMM1__PC2 EQU CYREG_GPIO_PRT0_PC2
COMM1__PORT EQU 0
COMM1__PS EQU CYREG_GPIO_PRT0_PS
COMM1__SHIFT EQU 3

/* COMM2 */
COMM2__0__DR EQU CYREG_GPIO_PRT1_DR
COMM2__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
COMM2__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
COMM2__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
COMM2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
COMM2__0__HSIOM_MASK EQU 0x0000F000
COMM2__0__HSIOM_SHIFT EQU 12
COMM2__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM2__0__INTR EQU CYREG_GPIO_PRT1_INTR
COMM2__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM2__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
COMM2__0__MASK EQU 0x08
COMM2__0__PC EQU CYREG_GPIO_PRT1_PC
COMM2__0__PC2 EQU CYREG_GPIO_PRT1_PC2
COMM2__0__PORT EQU 1
COMM2__0__PS EQU CYREG_GPIO_PRT1_PS
COMM2__0__SHIFT EQU 3
COMM2__DR EQU CYREG_GPIO_PRT1_DR
COMM2__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
COMM2__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
COMM2__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
COMM2__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM2__INTR EQU CYREG_GPIO_PRT1_INTR
COMM2__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM2__INTSTAT EQU CYREG_GPIO_PRT1_INTR
COMM2__MASK EQU 0x08
COMM2__PC EQU CYREG_GPIO_PRT1_PC
COMM2__PC2 EQU CYREG_GPIO_PRT1_PC2
COMM2__PORT EQU 1
COMM2__PS EQU CYREG_GPIO_PRT1_PS
COMM2__SHIFT EQU 3

/* COMM3 */
COMM3__0__DR EQU CYREG_GPIO_PRT1_DR
COMM3__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
COMM3__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
COMM3__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
COMM3__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
COMM3__0__HSIOM_MASK EQU 0x00000F00
COMM3__0__HSIOM_SHIFT EQU 8
COMM3__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM3__0__INTR EQU CYREG_GPIO_PRT1_INTR
COMM3__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM3__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
COMM3__0__MASK EQU 0x04
COMM3__0__PC EQU CYREG_GPIO_PRT1_PC
COMM3__0__PC2 EQU CYREG_GPIO_PRT1_PC2
COMM3__0__PORT EQU 1
COMM3__0__PS EQU CYREG_GPIO_PRT1_PS
COMM3__0__SHIFT EQU 2
COMM3__DR EQU CYREG_GPIO_PRT1_DR
COMM3__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
COMM3__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
COMM3__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
COMM3__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM3__INTR EQU CYREG_GPIO_PRT1_INTR
COMM3__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
COMM3__INTSTAT EQU CYREG_GPIO_PRT1_INTR
COMM3__MASK EQU 0x04
COMM3__PC EQU CYREG_GPIO_PRT1_PC
COMM3__PC2 EQU CYREG_GPIO_PRT1_PC2
COMM3__PORT EQU 1
COMM3__PS EQU CYREG_GPIO_PRT1_PS
COMM3__SHIFT EQU 2

/* Clock */
Clock__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL4
Clock__DIV_ID EQU 0x00000041
Clock__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1
Clock__PA_DIV_ID EQU 0x000000FF
Clock_2__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL6
Clock_2__DIV_ID EQU 0x00000042
Clock_2__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL2
Clock_2__PA_DIV_ID EQU 0x000000FF

/* TIMER */
TIMER_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT0_CC
TIMER_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT0_CC_BUFF
TIMER_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT0_COUNTER
TIMER_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT0_CTRL
TIMER_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT0_INTR
TIMER_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT0_INTR_MASK
TIMER_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT0_INTR_MASKED
TIMER_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT0_INTR_SET
TIMER_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT0_PERIOD
TIMER_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT0_PERIOD_BUFF
TIMER_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT0_STATUS
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x01
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 0
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x100
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 8
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x1000000
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 24
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x10000
TIMER_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 16
TIMER_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
TIMER_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x01
TIMER_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 0
TIMER_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
TIMER_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x01
TIMER_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 0
TIMER_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 0
TIMER_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT0_TR_CTRL0
TIMER_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT0_TR_CTRL1
TIMER_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT0_TR_CTRL2

/* BUZZ_F */
BUZZ_F__0__DR EQU CYREG_GPIO_PRT1_DR
BUZZ_F__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
BUZZ_F__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
BUZZ_F__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
BUZZ_F__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
BUZZ_F__0__HSIOM_MASK EQU 0x000000F0
BUZZ_F__0__HSIOM_SHIFT EQU 4
BUZZ_F__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
BUZZ_F__0__INTR EQU CYREG_GPIO_PRT1_INTR
BUZZ_F__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
BUZZ_F__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
BUZZ_F__0__MASK EQU 0x02
BUZZ_F__0__PC EQU CYREG_GPIO_PRT1_PC
BUZZ_F__0__PC2 EQU CYREG_GPIO_PRT1_PC2
BUZZ_F__0__PORT EQU 1
BUZZ_F__0__PS EQU CYREG_GPIO_PRT1_PS
BUZZ_F__0__SHIFT EQU 1
BUZZ_F__DR EQU CYREG_GPIO_PRT1_DR
BUZZ_F__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
BUZZ_F__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
BUZZ_F__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
BUZZ_F__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
BUZZ_F__INTR EQU CYREG_GPIO_PRT1_INTR
BUZZ_F__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
BUZZ_F__INTSTAT EQU CYREG_GPIO_PRT1_INTR
BUZZ_F__MASK EQU 0x02
BUZZ_F__PC EQU CYREG_GPIO_PRT1_PC
BUZZ_F__PC2 EQU CYREG_GPIO_PRT1_PC2
BUZZ_F__PORT EQU 1
BUZZ_F__PS EQU CYREG_GPIO_PRT1_PS
BUZZ_F__SHIFT EQU 1

/* IN_1MS */
IN_1MS__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
IN_1MS__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
IN_1MS__INTC_MASK EQU 0x4000
IN_1MS__INTC_NUMBER EQU 14
IN_1MS__INTC_PRIOR_MASK EQU 0xC00000
IN_1MS__INTC_PRIOR_NUM EQU 3
IN_1MS__INTC_PRIOR_REG EQU CYREG_CM0P_IPR3
IN_1MS__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
IN_1MS__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

/* LEDCLK */
LEDCLK__0__DR EQU CYREG_GPIO_PRT1_DR
LEDCLK__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LEDCLK__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LEDCLK__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LEDCLK__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
LEDCLK__0__HSIOM_MASK EQU 0x00F00000
LEDCLK__0__HSIOM_SHIFT EQU 20
LEDCLK__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDCLK__0__INTR EQU CYREG_GPIO_PRT1_INTR
LEDCLK__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDCLK__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LEDCLK__0__MASK EQU 0x20
LEDCLK__0__PC EQU CYREG_GPIO_PRT1_PC
LEDCLK__0__PC2 EQU CYREG_GPIO_PRT1_PC2
LEDCLK__0__PORT EQU 1
LEDCLK__0__PS EQU CYREG_GPIO_PRT1_PS
LEDCLK__0__SHIFT EQU 5
LEDCLK__DR EQU CYREG_GPIO_PRT1_DR
LEDCLK__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LEDCLK__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LEDCLK__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LEDCLK__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDCLK__INTR EQU CYREG_GPIO_PRT1_INTR
LEDCLK__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDCLK__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LEDCLK__MASK EQU 0x20
LEDCLK__PC EQU CYREG_GPIO_PRT1_PC
LEDCLK__PC2 EQU CYREG_GPIO_PRT1_PC2
LEDCLK__PORT EQU 1
LEDCLK__PS EQU CYREG_GPIO_PRT1_PS
LEDCLK__SHIFT EQU 5

/* LEDDIO */
LEDDIO__0__DR EQU CYREG_GPIO_PRT1_DR
LEDDIO__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LEDDIO__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LEDDIO__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LEDDIO__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
LEDDIO__0__HSIOM_MASK EQU 0x000F0000
LEDDIO__0__HSIOM_SHIFT EQU 16
LEDDIO__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDDIO__0__INTR EQU CYREG_GPIO_PRT1_INTR
LEDDIO__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDDIO__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LEDDIO__0__MASK EQU 0x10
LEDDIO__0__PC EQU CYREG_GPIO_PRT1_PC
LEDDIO__0__PC2 EQU CYREG_GPIO_PRT1_PC2
LEDDIO__0__PORT EQU 1
LEDDIO__0__PS EQU CYREG_GPIO_PRT1_PS
LEDDIO__0__SHIFT EQU 4
LEDDIO__DR EQU CYREG_GPIO_PRT1_DR
LEDDIO__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LEDDIO__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LEDDIO__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LEDDIO__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDDIO__INTR EQU CYREG_GPIO_PRT1_INTR
LEDDIO__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDDIO__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LEDDIO__MASK EQU 0x10
LEDDIO__PC EQU CYREG_GPIO_PRT1_PC
LEDDIO__PC2 EQU CYREG_GPIO_PRT1_PC2
LEDDIO__PORT EQU 1
LEDDIO__PS EQU CYREG_GPIO_PRT1_PS
LEDDIO__SHIFT EQU 4

/* LEDSTB */
LEDSTB__0__DR EQU CYREG_GPIO_PRT1_DR
LEDSTB__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LEDSTB__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LEDSTB__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LEDSTB__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
LEDSTB__0__HSIOM_MASK EQU 0x0F000000
LEDSTB__0__HSIOM_SHIFT EQU 24
LEDSTB__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDSTB__0__INTR EQU CYREG_GPIO_PRT1_INTR
LEDSTB__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDSTB__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LEDSTB__0__MASK EQU 0x40
LEDSTB__0__PC EQU CYREG_GPIO_PRT1_PC
LEDSTB__0__PC2 EQU CYREG_GPIO_PRT1_PC2
LEDSTB__0__PORT EQU 1
LEDSTB__0__PS EQU CYREG_GPIO_PRT1_PS
LEDSTB__0__SHIFT EQU 6
LEDSTB__DR EQU CYREG_GPIO_PRT1_DR
LEDSTB__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
LEDSTB__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
LEDSTB__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
LEDSTB__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDSTB__INTR EQU CYREG_GPIO_PRT1_INTR
LEDSTB__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
LEDSTB__INTSTAT EQU CYREG_GPIO_PRT1_INTR
LEDSTB__MASK EQU 0x40
LEDSTB__PC EQU CYREG_GPIO_PRT1_PC
LEDSTB__PC2 EQU CYREG_GPIO_PRT1_PC2
LEDSTB__PORT EQU 1
LEDSTB__PS EQU CYREG_GPIO_PRT1_PS
LEDSTB__SHIFT EQU 6

/* CapSense */
CapSense_Cmod__0__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Cmod__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Cmod__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Cmod__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Cmod__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
CapSense_Cmod__0__HSIOM_MASK EQU 0x00000F00
CapSense_Cmod__0__HSIOM_SHIFT EQU 8
CapSense_Cmod__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__0__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__0__MASK EQU 0x04
CapSense_Cmod__0__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Cmod__0__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Cmod__0__PORT EQU 4
CapSense_Cmod__0__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Cmod__0__SHIFT EQU 2
CapSense_Cmod__Cmod__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Cmod__Cmod__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Cmod__Cmod__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Cmod__Cmod__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Cmod__Cmod__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__Cmod__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__Cmod__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__Cmod__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__Cmod__MASK EQU 0x04
CapSense_Cmod__Cmod__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Cmod__Cmod__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Cmod__Cmod__PORT EQU 4
CapSense_Cmod__Cmod__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Cmod__Cmod__SHIFT EQU 2
CapSense_Cmod__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Cmod__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Cmod__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Cmod__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Cmod__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__MASK EQU 0x04
CapSense_Cmod__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Cmod__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Cmod__PORT EQU 4
CapSense_Cmod__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Cmod__SHIFT EQU 2
CapSense_CSD__ADC_CTL EQU CYREG_CSD_ADC_CTL
CapSense_CSD__CMOD_PAD EQU 1
CapSense_CSD__CSD_CONFIG EQU CYREG_CSD_CONFIG
CapSense_CSD__CSD_INTR EQU CYREG_CSD_INTR
CapSense_CSD__CSD_INTR_SET EQU CYREG_CSD_INTR_SET
CapSense_CSD__CSD_NUMBER EQU 0
CapSense_CSD__CSD_STATUS EQU CYREG_CSD_STATUS
CapSense_CSD__CSDCMP EQU CYREG_CSD_CSDCMP
CapSense_CSD__CSH_TANK_PAD EQU 2
CapSense_CSD__CSHIELD_PAD EQU 4
CapSense_CSD__DEDICATED_IO0 EQU CapSense_CSD__CMOD_PAD
CapSense_CSD__HSCMP EQU CYREG_CSD_HSCMP
CapSense_CSD__INTR_MASK EQU CYREG_CSD_INTR_MASK
CapSense_CSD__REFGEN EQU CYREG_CSD_REFGEN
CapSense_CSD__RESULT_VAL1 EQU CYREG_CSD_RESULT_VAL1
CapSense_CSD__RESULT_VAL2 EQU CYREG_CSD_RESULT_VAL2
CapSense_CSD__SENSE_DUTY EQU CYREG_CSD_SENSE_DUTY
CapSense_CSD__SENSE_PERIOD EQU CYREG_CSD_SENSE_PERIOD
CapSense_CSD__SEQ_INIT_CNT EQU CYREG_CSD_SEQ_INIT_CNT
CapSense_CSD__SEQ_NORM_CNT EQU CYREG_CSD_SEQ_NORM_CNT
CapSense_CSD__SEQ_START EQU CYREG_CSD_SEQ_START
CapSense_CSD__SEQ_TIME EQU CYREG_CSD_SEQ_TIME
CapSense_CSD__SW_AMUXBUF_SEL EQU CYREG_CSD_SW_AMUXBUF_SEL
CapSense_CSD__SW_BYP_SEL EQU CYREG_CSD_SW_BYP_SEL
CapSense_CSD__SW_CMP_N_SEL EQU CYREG_CSD_SW_CMP_N_SEL
CapSense_CSD__SW_CMP_P_SEL EQU CYREG_CSD_SW_CMP_P_SEL
CapSense_CSD__SW_DSI_SEL EQU CYREG_CSD_SW_DSI_SEL
CapSense_CSD__SW_FW_MOD_SEL EQU CYREG_CSD_SW_FW_MOD_SEL
CapSense_CSD__SW_FW_TANK_SEL EQU CYREG_CSD_SW_FW_TANK_SEL
CapSense_CSD__SW_HS_N_SEL EQU CYREG_CSD_SW_HS_N_SEL
CapSense_CSD__SW_HS_P_SEL EQU CYREG_CSD_SW_HS_P_SEL
CapSense_CSD__SW_REFGEN_SEL EQU CYREG_CSD_SW_REFGEN_SEL
CapSense_CSD__SW_RES EQU CYREG_CSD_SW_RES
CapSense_CSD__SW_SHIELD_SEL EQU CYREG_CSD_SW_SHIELD_SEL
CapSense_CSD__VREF_EXT_PAD EQU 8
CapSense_IDACComp__CONFIG EQU CYREG_CSD_CONFIG
CapSense_IDACComp__IDAC EQU CYREG_CSD_IDACB
CapSense_IDACComp__POSITION EQU 1
CapSense_IDACMod__CONFIG EQU CYREG_CSD_CONFIG
CapSense_IDACMod__IDAC EQU CYREG_CSD_IDACA
CapSense_IDACMod__POSITION EQU 0
CapSense_ISR__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
CapSense_ISR__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
CapSense_ISR__INTC_MASK EQU 0x2000
CapSense_ISR__INTC_NUMBER EQU 13
CapSense_ISR__INTC_PRIOR_MASK EQU 0xC000
CapSense_ISR__INTC_PRIOR_NUM EQU 3
CapSense_ISR__INTC_PRIOR_REG EQU CYREG_CM0P_IPR3
CapSense_ISR__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
CapSense_ISR__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR
CapSense_ModClk__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL3
CapSense_ModClk__DIV_ID EQU 0x00000040
CapSense_ModClk__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0
CapSense_ModClk__PA_DIV_ID EQU 0x000000FF
CapSense_Sns__0__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
CapSense_Sns__0__HSIOM_MASK EQU 0xF0000000
CapSense_Sns__0__HSIOM_SHIFT EQU 28
CapSense_Sns__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__0__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__0__MASK EQU 0x80
CapSense_Sns__0__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__0__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__0__PORT EQU 3
CapSense_Sns__0__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__0__SHIFT EQU 7
CapSense_Sns__1__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__1__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__1__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__1__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__1__HSIOM EQU CYREG_HSIOM_PORT_SEL3
CapSense_Sns__1__HSIOM_MASK EQU 0x0F000000
CapSense_Sns__1__HSIOM_SHIFT EQU 24
CapSense_Sns__1__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__1__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__1__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__1__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__1__MASK EQU 0x40
CapSense_Sns__1__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__1__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__1__PORT EQU 3
CapSense_Sns__1__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__1__SHIFT EQU 6
CapSense_Sns__10__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__10__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__10__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__10__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__10__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_Sns__10__HSIOM_MASK EQU 0x000000F0
CapSense_Sns__10__HSIOM_SHIFT EQU 4
CapSense_Sns__10__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__10__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__10__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__10__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__10__MASK EQU 0x02
CapSense_Sns__10__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__10__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__10__PORT EQU 2
CapSense_Sns__10__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__10__SHIFT EQU 1
CapSense_Sns__2__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__2__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__2__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__2__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__2__HSIOM EQU CYREG_HSIOM_PORT_SEL3
CapSense_Sns__2__HSIOM_MASK EQU 0x00F00000
CapSense_Sns__2__HSIOM_SHIFT EQU 20
CapSense_Sns__2__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__2__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__2__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__2__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__2__MASK EQU 0x20
CapSense_Sns__2__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__2__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__2__PORT EQU 3
CapSense_Sns__2__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__2__SHIFT EQU 5
CapSense_Sns__3__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__3__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__3__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__3__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__3__HSIOM EQU CYREG_HSIOM_PORT_SEL3
CapSense_Sns__3__HSIOM_MASK EQU 0x000F0000
CapSense_Sns__3__HSIOM_SHIFT EQU 16
CapSense_Sns__3__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__3__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__3__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__3__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__3__MASK EQU 0x10
CapSense_Sns__3__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__3__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__3__PORT EQU 3
CapSense_Sns__3__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__3__SHIFT EQU 4
CapSense_Sns__4__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__4__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__4__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__4__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__4__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_Sns__4__HSIOM_MASK EQU 0xF0000000
CapSense_Sns__4__HSIOM_SHIFT EQU 28
CapSense_Sns__4__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__4__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__4__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__4__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__4__MASK EQU 0x80
CapSense_Sns__4__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__4__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__4__PORT EQU 2
CapSense_Sns__4__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__4__SHIFT EQU 7
CapSense_Sns__5__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__5__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__5__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__5__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__5__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_Sns__5__HSIOM_MASK EQU 0x0F000000
CapSense_Sns__5__HSIOM_SHIFT EQU 24
CapSense_Sns__5__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__5__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__5__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__5__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__5__MASK EQU 0x40
CapSense_Sns__5__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__5__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__5__PORT EQU 2
CapSense_Sns__5__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__5__SHIFT EQU 6
CapSense_Sns__6__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__6__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__6__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__6__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__6__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_Sns__6__HSIOM_MASK EQU 0x00F00000
CapSense_Sns__6__HSIOM_SHIFT EQU 20
CapSense_Sns__6__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__6__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__6__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__6__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__6__MASK EQU 0x20
CapSense_Sns__6__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__6__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__6__PORT EQU 2
CapSense_Sns__6__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__6__SHIFT EQU 5
CapSense_Sns__7__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__7__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__7__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__7__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__7__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_Sns__7__HSIOM_MASK EQU 0x000F0000
CapSense_Sns__7__HSIOM_SHIFT EQU 16
CapSense_Sns__7__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__7__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__7__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__7__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__7__MASK EQU 0x10
CapSense_Sns__7__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__7__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__7__PORT EQU 2
CapSense_Sns__7__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__7__SHIFT EQU 4
CapSense_Sns__8__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__8__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__8__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__8__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__8__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_Sns__8__HSIOM_MASK EQU 0x0000F000
CapSense_Sns__8__HSIOM_SHIFT EQU 12
CapSense_Sns__8__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__8__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__8__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__8__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__8__MASK EQU 0x08
CapSense_Sns__8__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__8__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__8__PORT EQU 2
CapSense_Sns__8__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__8__SHIFT EQU 3
CapSense_Sns__9__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__9__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__9__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__9__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__9__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_Sns__9__HSIOM_MASK EQU 0x00000F00
CapSense_Sns__9__HSIOM_SHIFT EQU 8
CapSense_Sns__9__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__9__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__9__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__9__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__9__MASK EQU 0x04
CapSense_Sns__9__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__9__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__9__PORT EQU 2
CapSense_Sns__9__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__9__SHIFT EQU 2
CapSense_Sns__SW1_Sns0__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__SW1_Sns0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__SW1_Sns0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__SW1_Sns0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__SW1_Sns0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW1_Sns0__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW1_Sns0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW1_Sns0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW1_Sns0__MASK EQU 0x80
CapSense_Sns__SW1_Sns0__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__SW1_Sns0__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__SW1_Sns0__PORT EQU 3
CapSense_Sns__SW1_Sns0__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__SW1_Sns0__SHIFT EQU 7
CapSense_Sns__SW10_Sns0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__SW10_Sns0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__SW10_Sns0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__SW10_Sns0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__SW10_Sns0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW10_Sns0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW10_Sns0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW10_Sns0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW10_Sns0__MASK EQU 0x04
CapSense_Sns__SW10_Sns0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__SW10_Sns0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__SW10_Sns0__PORT EQU 2
CapSense_Sns__SW10_Sns0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__SW10_Sns0__SHIFT EQU 2
CapSense_Sns__SW11_Sns0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__SW11_Sns0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__SW11_Sns0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__SW11_Sns0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__SW11_Sns0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW11_Sns0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW11_Sns0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW11_Sns0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW11_Sns0__MASK EQU 0x02
CapSense_Sns__SW11_Sns0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__SW11_Sns0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__SW11_Sns0__PORT EQU 2
CapSense_Sns__SW11_Sns0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__SW11_Sns0__SHIFT EQU 1
CapSense_Sns__SW2_Sns0__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__SW2_Sns0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__SW2_Sns0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__SW2_Sns0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__SW2_Sns0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW2_Sns0__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW2_Sns0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW2_Sns0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW2_Sns0__MASK EQU 0x40
CapSense_Sns__SW2_Sns0__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__SW2_Sns0__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__SW2_Sns0__PORT EQU 3
CapSense_Sns__SW2_Sns0__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__SW2_Sns0__SHIFT EQU 6
CapSense_Sns__SW3_Sns0__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__SW3_Sns0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__SW3_Sns0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__SW3_Sns0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__SW3_Sns0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW3_Sns0__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW3_Sns0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW3_Sns0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW3_Sns0__MASK EQU 0x20
CapSense_Sns__SW3_Sns0__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__SW3_Sns0__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__SW3_Sns0__PORT EQU 3
CapSense_Sns__SW3_Sns0__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__SW3_Sns0__SHIFT EQU 5
CapSense_Sns__SW4_Sns0__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__SW4_Sns0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__SW4_Sns0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__SW4_Sns0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__SW4_Sns0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW4_Sns0__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW4_Sns0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__SW4_Sns0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__SW4_Sns0__MASK EQU 0x10
CapSense_Sns__SW4_Sns0__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__SW4_Sns0__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__SW4_Sns0__PORT EQU 3
CapSense_Sns__SW4_Sns0__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__SW4_Sns0__SHIFT EQU 4
CapSense_Sns__SW5_Sns0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__SW5_Sns0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__SW5_Sns0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__SW5_Sns0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__SW5_Sns0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW5_Sns0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW5_Sns0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW5_Sns0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW5_Sns0__MASK EQU 0x80
CapSense_Sns__SW5_Sns0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__SW5_Sns0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__SW5_Sns0__PORT EQU 2
CapSense_Sns__SW5_Sns0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__SW5_Sns0__SHIFT EQU 7
CapSense_Sns__SW6_Sns0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__SW6_Sns0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__SW6_Sns0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__SW6_Sns0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__SW6_Sns0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW6_Sns0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW6_Sns0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW6_Sns0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW6_Sns0__MASK EQU 0x40
CapSense_Sns__SW6_Sns0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__SW6_Sns0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__SW6_Sns0__PORT EQU 2
CapSense_Sns__SW6_Sns0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__SW6_Sns0__SHIFT EQU 6
CapSense_Sns__SW7_Sns0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__SW7_Sns0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__SW7_Sns0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__SW7_Sns0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__SW7_Sns0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW7_Sns0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW7_Sns0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW7_Sns0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW7_Sns0__MASK EQU 0x20
CapSense_Sns__SW7_Sns0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__SW7_Sns0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__SW7_Sns0__PORT EQU 2
CapSense_Sns__SW7_Sns0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__SW7_Sns0__SHIFT EQU 5
CapSense_Sns__SW8_Sns0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__SW8_Sns0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__SW8_Sns0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__SW8_Sns0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__SW8_Sns0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW8_Sns0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW8_Sns0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW8_Sns0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW8_Sns0__MASK EQU 0x10
CapSense_Sns__SW8_Sns0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__SW8_Sns0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__SW8_Sns0__PORT EQU 2
CapSense_Sns__SW8_Sns0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__SW8_Sns0__SHIFT EQU 4
CapSense_Sns__SW9_Sns0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_Sns__SW9_Sns0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_Sns__SW9_Sns0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_Sns__SW9_Sns0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_Sns__SW9_Sns0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW9_Sns0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW9_Sns0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_Sns__SW9_Sns0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_Sns__SW9_Sns0__MASK EQU 0x08
CapSense_Sns__SW9_Sns0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_Sns__SW9_Sns0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_Sns__SW9_Sns0__PORT EQU 2
CapSense_Sns__SW9_Sns0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_Sns__SW9_Sns0__SHIFT EQU 3

/* Miscellaneous */
CYDEV_BCLK__HFCLK__HZ EQU 24000000
CYDEV_BCLK__HFCLK__KHZ EQU 24000
CYDEV_BCLK__HFCLK__MHZ EQU 24
CYDEV_BCLK__SYSCLK__HZ EQU 24000000
CYDEV_BCLK__SYSCLK__KHZ EQU 24000
CYDEV_BCLK__SYSCLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PSOC4A EQU 18
CYDEV_CHIP_DIE_PSOC5LP EQU 2
CYDEV_CHIP_DIE_PSOC5TM EQU 3
CYDEV_CHIP_DIE_TMA4 EQU 4
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_FM0P EQU 5
CYDEV_CHIP_FAMILY_FM3 EQU 6
CYDEV_CHIP_FAMILY_FM4 EQU 7
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_PSOC6 EQU 4
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x1B2811AB
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 18
CYDEV_CHIP_MEMBER_4D EQU 13
CYDEV_CHIP_MEMBER_4E EQU 6
CYDEV_CHIP_MEMBER_4F EQU 19
CYDEV_CHIP_MEMBER_4G EQU 4
CYDEV_CHIP_MEMBER_4H EQU 17
CYDEV_CHIP_MEMBER_4I EQU 23
CYDEV_CHIP_MEMBER_4J EQU 14
CYDEV_CHIP_MEMBER_4K EQU 15
CYDEV_CHIP_MEMBER_4L EQU 22
CYDEV_CHIP_MEMBER_4M EQU 21
CYDEV_CHIP_MEMBER_4N EQU 10
CYDEV_CHIP_MEMBER_4O EQU 7
CYDEV_CHIP_MEMBER_4P EQU 20
CYDEV_CHIP_MEMBER_4Q EQU 12
CYDEV_CHIP_MEMBER_4R EQU 8
CYDEV_CHIP_MEMBER_4S EQU 11
CYDEV_CHIP_MEMBER_4T EQU 9
CYDEV_CHIP_MEMBER_4U EQU 5
CYDEV_CHIP_MEMBER_4V EQU 16
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_5B EQU 2
CYDEV_CHIP_MEMBER_6A EQU 24
CYDEV_CHIP_MEMBER_FM3 EQU 28
CYDEV_CHIP_MEMBER_FM4 EQU 29
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4K
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1
CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_6A_ES EQU 17
CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33
CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4K_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DFT_SELECT_CLK0 EQU 8
CYDEV_DFT_SELECT_CLK1 EQU 9
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA EQU 5
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD EQU 5
CYDEV_VDDD_MV EQU 5000
CYDEV_WDT_GENERATE_ISR EQU 1
CYIPBLOCK_m0s8cpussv3_VERSION EQU 1
CYIPBLOCK_m0s8csdv2_VERSION EQU 1
CYIPBLOCK_m0s8ioss_VERSION EQU 1
CYIPBLOCK_m0s8lcd_VERSION EQU 2
CYIPBLOCK_m0s8lpcomp_VERSION EQU 2
CYIPBLOCK_m0s8pass4a_VERSION EQU 1
CYIPBLOCK_m0s8peri_VERSION EQU 1
CYIPBLOCK_m0s8scb_VERSION EQU 2
CYIPBLOCK_m0s8tcpwm_VERSION EQU 2
CYIPBLOCK_m0s8wco_VERSION EQU 1
CYIPBLOCK_s8srsslt_VERSION EQU 1
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
